The present invention relates to asynchronous system architectures with orders greater than single-issue.
The goal of a dual issue system in a processor architecture is to be able to execute two instructions per cycle. This is accomplished with two parallel pipelines for handling the tasks for each of a pair of instructions. In the standard synchronous design, a pair of instructions are simultaneously received each clock cycle. Because of the interdependency between instructions and the limitation that the instructions be issued simultaneously (i.e., at only one time in each clock cycle), there are inherent system complexities which prevent system performance from approaching the desired goal. That is, when the instructions are issued simultaneously, there are issues relating to program order and data dependency which require complex schemes for determining, for example, whether two instructions may be executed at the same time. These complex schemes not only hamper system performance, but make multiple issue architectures difficult to verify.
It is therefore desirable to provide circuits and techniques by which multiple and mixed-order-issue system architectures may be more readily implemented.